I had the chance recently to speak with Cadence’s Rahul Deokar, Product Management Director of the company’s Digital Implementation Group, about the future of the foundry ecosystem. Below is the first in a three-part series from our discussion.
Thanks for taking the time to speak with me, Rahul. I know the Voices readers will be excited to hear from you! First off, can you tell me about your role at Cadence?
Of course, thank you for having me! My team is responsible for working with foundry and IP partners on advanced node technology collaborations. It’s our goal to establish industry proof-points and to help customers in the adoption of 14nm design.
From Cadence’s perspective, why is early collaboration at 14nm so critical to silicon success?
When creating a complete enablement package for a new process node, we’ve found, based on our experience at 28nm and 20nm, that it’s critically important to have a vertical approach to collaboration. This has become even truer for 14nm FinFET technology. To create a viable offering, all the elements of enablement – including process, cell library, EDA, and IP – must be optimized with respect to the other elements.
As the manufacturing process evolves into a yielding node, the enablement package must track to the changes. Because of the mutual dependence, one element cannot change without affecting the other elements. That’s why the industry must work closely together, starting from the beginning, to ensure silicon success.
Speaking of FinFET technology, what do you think designers will do with all the capacity, improved performance and power savings that it will bring?
History proves that when new technologies are available, people find innovative ways to use them to create new and often unexpected value. FinFETs can potentially enable the next leap forward for mobile devices, cloud infrastructure, and the “Internet of Things.” That’s just one more reason why the early and continuous collaboration with the ecosystem is absolutely essential to unleash this semiconductor innovation.
What prevents designers from migrating to 14nm when it promises so many benefits?
FinFET technology pushes the fundamental performance and power characteristics that planar transistors exhibited at 20nm, and takes it to new levels. That’s because a FinFET gate wraps over the conducting drain-source channel. This results in better electrical properties, providing lower threshold voltages and better performance as well as reductions in both leakage and dynamic power. You can read more about it in our announcement from December 2012. FinFET’s are definitely propelling the semiconductor industry towards a strong cycle of product innovation and growth.
However, the combination of new device types, 193nm wavelength lithography, resulting manufacturing-based rules, and materials physics are creating new technical and collaboration challenges. These require changes to custom/analog and digital implementation flows, as well as parasitic extraction and signoff. Given all the challenges, Cadence expects that the EDA industry may collectively spend up to $1.6 billion for design tool R&D at 20/16/14nm combined.
Curious to hear what the industry is doing to overcome these challenges? Be sure to check back for the second part of my conversation with Rahul, who will elaborate on Cadence’s 14nm/FinFET efforts.