Collaboration – A Critical Link to Successful 32nm ASIC Designs

The successful tape-out of a new chip design is always something to celebrate.  It’s the culmination of months of intensive teamwork, late nights, lots of caffeine and more conference calls than can be counted. With the race to bring 32/28nm low-power system-on-chip (SoC) designs to market in full swing, our ASIC design center has been the epicenter of several such projects. This EE Times piece on overcoming 32/28nm implementation challenges does a good job of outlining the complexity of this type of rollout.

             How do you turn a customer’s brain-child into a reality? The collaborative effort between the customer, the foundry, and other partners has never been so important as it is with early designs at the 32/28nm low-power process node.  Early adopters of new technology always face obstacles as pioneers implementing new design flows and IP into increasingly complex SoC designs. These issues are compounded in an ASIC flow where IP comes from various sources and the customer defining the netlist may have different tools than the ASIC design center doing the back-end design.

             Recently, our ASIC design center tackled a 32nn LP High-k Metal Gate (HKMG) SoC tape-out project that had all the elements described above; a new EDA   vendor-tool flow, IP designed by our customer, IP partners and Samsung IP using different verification tools, and the usual bugs that come with new tools, IP and design kits. In spite of all these complications, the tape out was a success largely as a result of great teamwork. With EDA field application engineers working side-by-side with Samsung’s and the customer’s engineers throughout the entire project, potential issues were resolved quickly and efficiently. For example, issues arose in the definition of multi-power domains that required both tool bug fixes and netlist corrections. Having on site EDA field application engineers facilitated problem solving to fix the bugs and the netlist concurrently. Also, customer designed IP was verified with different tools than those used for full-chip verification creating layout versus schematic (LVS) errors in the final design. The Place and Route and verification tools were synchronized and ran successfully with reduced iterations. Teamwork and collaboration were essential in overcoming these and other issues the design team faced.

             This successful 32nm HKMG low-power design would not have been possible without the dedication and open collaboration of all the parties involved. There are going to be a lot of interesting case studies coming out over the next couple of months on 32/28nm LP design starts. If you’re designer working on such as project, leave me a comment as I’d like to hear about some of the challenges you’re facing and of course, the creative solutions used to overcome those issues.