I had the chance recently to speak with Cadence’s Rahul Deokar, Product Management Director of the company’s Digital Implementation Group, about the future of the foundry ecosystem. Below is the second in a three-part series from our discussion. And if you missed it, be sure to check out Part 1 .
What are the biggest factors impacting Cadence’s 14nm/FinFET efforts, from the custom IP and standard cell design aspect?
Our 14nm and FinFET efforts are pretty extensive. In my opinion, the design domain has the biggest impact on these efforts, as examined in this comprehensive 14nm whitepaper.
First of all, the design strategies that custom and analog designers have used in the past will no longer work. For example, with planar transistors, standard cell designers can arbitrarily change transistor width in order to manage drive current. With FinFETs, designers cannot do this – they can only add or subtract fins to change the drive current.
Secondly, another challenge for the custom designer is parasitic resistance and capacitance. As the device shrinks further on the horizontal plane, and at the same time “rises” in the z-axis dimension, new coupling to neighboring elements appear and create additional parasitic challenges. Capacitance gate-to-source (Cgs) and capacitance gate-to-drain (Cgd) effects become an even larger concern, and contribute to the Miller Effect. Also, additional parasitic resistors in the source/drain area affect device performance.
What is Cadence doing to help solve these challenges?
What’s needed is a design methodology that very quickly enables the designer to see the effects of these elements on the performance of the circuit that is being developed. The Cadence Virtuoso platform and library characterization tools have been enhanced to address all of these custom design challenges.
What do designers need to know about digital design at 14nm?
Digital designers will face new and more complex design rules – for starters, double-patterning colorization requirements, and more restrictions on access to cells and pins. It’s important for designers to remember that floor-planning, placement, routing, parasitic extraction, and electrical and physical signoff should be double patterning-correct. This means that all metal topologies in the design are validated to be free of double patterning conflicts such as odd-cycle conflicts or metal layers that violate SAMEMASK rules in the LEF file.
One particular step in floor-planning that is important is power planning, the ability to validate that all power routing is free of double patterning violations in relation to other power routes as well as hard macros. Also, standard cell and hard macro pins, if colorized, must be separated in accordance to SAMEMASK rules, meaning that metal shapes of the same color must not be in adjacent tracks.
One important aspect of 14nm routing is that the difference in resistance between a lower metal layer such as M1 or M2 can be 50x or more compared to higher metal layers like M7 or M8. Therefore, routes that traverse a long distance should be routed using higher metal layers as long as there are tracks available. For short-distance routes or routes in highly congested regions, this becomes less of an option because of the high usage of vias in that route. An optimization engine should take routing layers into account in order to leverage higher metal layers to reduce net delays.
Be sure to check back for more of my discussion with Rahul, who will provide insight on the ARM® Cortex™-A7 tape-out on Samsung’s 14nm FinFET process.