Part 3 – An Inside Look at 14nm (Q&A with Cadence)

Posted on 09/20/2013 by

Samsung Foundry

I had the chance recently to speak with Cadence’s Rahul Deokar, Product Management Director of the company’s Digital Implementation Group, about the future of the foundry ecosystem. Below is the third in a three-part series from our discussion. And if you missed them, be sure to check out Part 1 and Part 2 .

Can you shed more light on the ARM® Cortex™-A7 tape-out on Samsung’s 14nm FinFET process, and how does it help customers?

Sure. Last year, Cadence, along with Samsung and ARM, announced the tape-out of the first 14nm test chip implementation of the high-performance ARM® Cortex™-A7 processor, the most energy-efficient applications processor from ARM, on Samsung’s 14-nanometer FinFET process. Most test chips for new processes are small design-structures, but that’s not sufficient to give a good feel for the big designs that engineers have to deal with later in production. So in this case, using ARM’s Cortex™-A7 processor on the test chip was a giant stride forward for the industry. It gave us additional insight that small design-structures cannot.

What’s the significance of this?

Designed with a complete Cadence® RTL-to-signoff flow, the chip was the first to target Samsung’s 14nm FinFET process. It accelerated the continuing move to high-density, high-performance and ultra-low power SoCs for future smartphones, tablets and all other advanced mobile devices. Our common goal in such collaborations is to enable our customers to reap the benefits and competitive advantages of designing at the most advanced technologies.

So what was learned from the experience of the 14nm test-chip?

It takes a village. No single company has everything that is needed for design acceleration at advanced nodes. It was necessary for Cadence, ARM and Samsung to work together and work earlier in the design cycle to bring this test chip to fruition. That’s the biggest learning here.

I think this tight collaboration model needs to continue going forward. This is the only way the risk of new process node adoption can be mitigated for all our mutual customers.

What will come out of this test-chip experience?

The test chip exercise provided a lot of opportunities for co-optimizing the value-chain. It required a deeper and earlier level of collaboration compared to previous process nodes. The earlier the collaboration, the more each participant can influence the other in making the most optimal choices in the process, the design IP, and the EDA flow.

By engaging at the early stages of process development, mutual customers designing with the new node can also get started sooner. Now that we’ve gone through this process and saw how successful it was, we will definitely take what we learned from this test-chip experience, and apply the learnings to our future collaborations.

Anything else to add or parting advice?

I think we covered everything. I just want to thank Samsung for your continued support and collaboration. You’ve been a great partner, and we are excited for all the future collaborations on the horizon. Also, I want to encourage the Voices readers to take a minute and watch this informative Samsung, ARM, Cadence panel discussion. Thanks for having me!


Tags: , , , , , ,

Leave a Reply

Your email address will not be published. Required fields are marked *

Captcha *