14nm FinFET is a hot topic at the moment. But, there are other advanced process technologies that engineers should also consider, particularly, if the application requires an extreme low-power chip design.
FD-SOI is one of those unique technologies that allows for the continuation of Moore’s Law with an upgrade to traditional planar semiconductor process technology. This particular version of FD-SOI delivers a nice balance of higher performance with low power and is well suited for mobile, consumer electronics and IT infrastructure applications.
The SOI Consortium is hosting a FD-SOI workshop on Friday, Feb. 27 at the Palace Hotel in San Francisco. I’ll be giving a presentation as well as sitting on a panel. Please join us for lively conversation on how to get the most out of an FD-SOI design. I look forward to seeing you at the workshop.
Are you considering a FD-SOI chip design? If so, I’d like to hear your thoughts.
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