Recently, we asked Bob O’Donnell, president and chief analyst of TECHnalysis Research, LLC, to provide his take on the transition to the new Gate-All-Around transistor structure. By rethinking and rearchitecting the basic transistor design, Bob pens that the tech industry can look forward to several generations of improvements in process technology with reductions in semiconductor size and power requirements, as well as increases in semiconductor performance. Read on to see what Bob has to say. You can also follow him on Twitter @bobodtech.
Anyone who follows the semiconductor industry to even the slightest degree has undoubtedly heard recently that that the rate of chip performance increases has started to slow. At the same time, companies who build these chips have discussed some of the challenges they’re facing in trying to reduce the size of the chips they are manufacturing. Though commonly associated with the decline of Moore’s Law, the factors impacting these performances increase slowdowns and semiconductor process node size reductions are several fold. Seemingly done in by fundamental laws of physics, as well as economic realities, the entire electronics industry has been bracing for an impact that many fear could slow down the rapid pace of innovation to which it has become accustomed. But not everyone is ready to throw in the towel on transistor level advancements just yet. In fact, only a few months back Samsung Semiconductor’s foundry business announced a significant new advance in transistor design called Gate -All- Around, or GAA, that promises to keep the transistor-level semiconductor advances moving forward for several years to come. Fundamentally, GAA provides a rethinking and rearchitecting of basic transistor design in which the silicon channel inside a transistor is completely encircled by gate material instead of having it be covered by gate material on just three sides as with current FinFET designs. The two key benefits of this design reductions, and more potential for channel length scaling, which can increase transistor density.
Practically speaking, this means the overall tech industry can look forward to several generations of improvements in process technology. These advancements will bring reductions in semiconductor size and power requirements, as well as increases in semiconductor performance. Together with Extreme UltraViolet (EUV) lithography—considered the next major technology advance in semiconductor fabrication—this gives the chip industry a clear path from 7nm past 5nm and onto 3nm process nodes. In other words, the tech industry is safe from any significant slowdowns in innovation on the semiconductor side and can count on the chips it needs to power increasingly capable and sophisticated generations of products, for many years to come.
Technically speaking, this also provides a way for the semiconductor foundry business to move past FinFET designs thanks to the reduced voltage enabled by GAA FET technology. As transistors have continued to shrink, voltage scaling has proven to be one of the most challenging problems to overcome, but the new design approach taken with GAA reduces the issue. A key benefit to the GAA transistor is the ability to reduce power consumption due to voltage scaling, while still improving performance. The specific timelines for those improvements may not come as quickly as the industry has seen in the past, but at least the uncertainty around whether or not they were going to come can now fade away. For both chip and device makers, these technology advancements provide a much clearer view into the future of semiconductor manufacturing and should give them the confidence they need to move forward with aggressive long-term product plans.
The timing of the GAA enhancements is fortuitous for the tech industry, as well. Up until recently, most advancement in the semiconductor industry have been focused on individual chips or monolithic SOC (system on chip) designs that are all based on silicon dies built off a single process node size. Certainly GAA will provide important benefits for these types of semiconductors. In addition, however, as increasing momentum builds around new “chiplet” SOC designs that combine several smaller chip components that can be built at different process nodes, it could be easily misinterpreted that transistor-level enhancements don’t carry as much value. In fact, some might argue that as monolithic SOCs are broken apart into smaller pieces, there is less need for smaller manufacturing process nodes. The truth, however, is more complex and more nuanced. For chiplet-based designs to truly succeed, the industry needs both improved process technology for certain chiplet components, and improvements in packaging and interconnect to link those elements and all the other chiplet components together. It’s important to remember that the most advanced chiplet components are becoming increasingly sophisticated. These new designs demand the transistor density that 3mm GAA manufacturing can provide. The rise in AI-specific accelerators, for example, along with increasingly sophisticated CPU, GPU, FPGA architectures need all the processing horsepower they can muster. As a result, while we will undoubtedly continue to see certain semiconductor components stop their incessant march down the process node roadmaps and settle in at larger process sizes, the need for continued process shrinks on these key components remains unabated.
The tech industry’s dependence on semiconductor performance improvements has become so embedded that the potential slowdown in process technologies has caused a fair amount of concern and even negative press about what the possible impacts to the overall tech world could be. While even the advancements enabled by GAA don’t get the industry completely past some of the issues that have started to surface, they are significant enough that they provide the kind of breathing room the industry needs to keep its developments moving forward. Plus, they offer the clever engineers who came up with the ideas and technologies behind GAA a bit more time to figure out the next advancement they need to keep the process moving yet again.