What to Expect at 20nm

Do you have plans to start a 20nm design in 2011? If so, please leave a comment below with your thoughts.

According to Moore’s Law, the density of a chip will double approximately every two years. However, a recent article on semiconductor trends suggests that with the exception of Samsung and Intel, Moore’s Law is slowing down to a halt. This in turn begs the question, will this happen?

I am continually impressed on how far innovation has brought us and am convinced consumer demand for applications requiring ever increasing performance will motivate companies to find a way to keep Moore’s Law marching forward. Chips in production today at 45/40nm are reaching transistor counts of 2 to 3 billion! 32/28nm designs in sampling stages now will double that figure. Two weeks ago, the Common Platform alliance, a collaboration and partnership between IBM, Samsung and GLOBALFOUNDRIES, disclosed details regarding the roll-out of 20nm process technology which will enable the transistor count to roughly double yet again.

What can designers expect from Samsung at 20nm? 

Our focus for this process technology generation is to maintain the same increases in performance, power efficiency, and density that we’ve seen moving from 45nm to 32/28nm with the addition of High k Metal Gate (HKMG). Our 20nm technology will be a full node shrink from 28nm, enabling the ~50% area scaling that the industry has come to expect with each technology generation. The technology has been designed to allow us to maintain our leadership in die size and cost, which remain critical factors for customers at leading-edge nodes.

Some of the distinguishing features of 20nm HKMG include:

  • A build on the HKMG materials & integration concepts qualified at 32nm  
  • Planar bulk CMOS technology will be used with second-generation gate last approach to HKMG
  • 193nm immersion lithography will be supplemented by source-mask optimization constrained minimum pitch to reduce the need for time-consuming, costly double-patterning
  • Second-generation ultra-low k dielectrics will be employed to lower power dissipation by reducing interconnect capacitance and wiring delay
  • Innovation with local interconnect and self-aligned vias to achieve cell-level scaling and elimination of a metal layer
  • Fifth-generation strained silicon technology will be integrated for power and heat reduction and more efficient switching
  • 30% improvement in performance over 28LP at the same standby current

The 20nm technology is ideally suited for a broad range of high performance and power-sensitive devices, including chips designed for smartphones, tablets, other portable consumer electronics as well as IT communications infrastructure.

Test-chip shuttles for customers will begin in the second half of this year. 

 Do you have plans to start a 20nm design in 2011? If so, please leave a comment below with your thoughts.